Electrical systems, such as communications systems, may use a timing source to generate a clock signal to synchronize the electrical system. Some electrical systems employ two timing sources, a working timing source and a protect timing source. The protect timing source is used by the electrical system, for example, when the working timing source becomes disabled.
While the electrical system is operational, it is desirable to seamlessly transition between the working and protect timing sources. However, if the clock signals from the working and protect timing sources are not substantially in phase, operation of the electrical system may be disrupted when transitioning between the two timing sources. For example, when a high data rate communications system transitions between the working and protect timing sources that do not have substantially in-phase clock signals, electrical system components, such as phase lock loops, may lose phase lock. As a result, a communications system may suffer from bit errors, including dropped frames.
This problem is particularly of concern in electrical systems in which the clock signals from the working and protect timing sources are distributed to different modules in a rack of the electrical system. The clock signals must be delivered in phase lock to each module to diminish bit error rates.
In one type of electrical system, the clock signals are serially coupled to each component. A conventional electrical system comprises working and protect tiing sources and components, such as slots. The working and protect timing sources respectively generate working and protect clock, or timing, signals. Modules may be inserted into the slots. The slots, and any modules inserted into the slots, are respectively coupled by first and second buses to the working and protect timing sources.
Each slot is typically coupled to the working and protect timing sources by segments of the first and second buses having different electrical lengths. As a result, the working and protect clock signals on the first and second buses are typically distributed out of phase to each module. In other words, a phase shift, or skew, between the working and protect clock signals typically arises at each module.
Furthermore, when inserted into a slot, each module capacitively loads the first and second buses. The capacitive loading arises because of capacitances at module terminals are coupled to the first and second buses. The capacitive loading typically aggravates the phase shift between the working and protect clock signals at each slot when differing electrical lengths of segments of the first and second buses connect a slot respectively with the working and protect timing sources. The increased phase shift, due to the capacitive loading, is dependent on the number and locations of the modules inserted into the slots of the electrical system. As a result, the phase of the clock signals from the working and protect timing sources may be further skewed. Hence, the likelihood that the operation of the electrical system will be disrupted is increased. Therefore, there is a need to maintain phase lock between the signals of the working and protect timing sources.